1. Field of the Invention
A device is disclosed comprising a semiconductor integrated circuit (IC) chip having disposed on it antenna and the circuitry for the IC chip, wherein antenna and the circuitry of the IC chip are integrated so as to provide the IC chip with an improved antenna effective area. The design of the antenna placement on the chip is independent of the location of the antenna on the chip. As a result, antenna-on-a-chips of this invention are simpler to design and manufacture than the designs disclosed in the prior art. With increasing dependence on local and wide area wireless networks, particularly those with low power (range) requirements and local sensing or object identification, there is a need to have an antenna structure integrated onto single semiconductor devices. One important lack has been an on-chip antenna structure that overcomes simple deficiencies of size.
The length and material of antennas normally determine the frequency and intensity of signals that may be received or sent from the antenna. However with smaller and smaller local area wireless networks being contemplated, the concept of a room sized network area or building area with antennas mounted in walls and ceilings (whether independent separate antennas or multi-use antennas, such as using electrical wiring or telephone wiring as an antenna structure), the feasibility of using very low power antenna structures to transfer information from a local network to a wireless IC device or system containing such wireless IC device becomes practicable.
2. Description of the Prior Art
It has been known to provide antennae and circuitry at specific locations on chips. U.S. Pat. Nos. 4,857,893 and 4,724,427 disclose the use of planar antennas that are included in circuitry of a transponder on a chip. As disclosed therein, the antenna coil is etched around the periphery of the chip substrate. In the center of the antenna coil are found a custom logic circuit, a programmable memory array, and memory control logic. The planar antenna of the transponder was said to employ a magnetic film inductor on the chip in order to allow for a reduction in the number of turns and thereby simplify fabrication of the inductors. It disclosed an antenna having a multi-turned spiral coil and having a 1 cm×1 cm outer diameter. When a high frequency current was passed in the coil, the magnetic films were said to be driven in a hard direction, and the two magnetic films around each conductor served as a magnetic core enclosing a one turn coil. The magnetic films were said to increase the inductance of the coil, in addition to its free-space inductance.
One of the problems with the approach as taught in U.S. Pat. Nos. 4,857,893 and 4,724,427 is the need to fabricate small, air core inductors of sufficiently high inductance and Q for integrated circuit applications. The small air core inductors were said to be made by depositing a permalloy magnetic film or other suitable material having a large magnetic permeability and electric insulating properties in order to increase the inductance L of the coil. Such an approach increases the complexity and cost of the antenna on a chip and also limits the ability to reduce the size of the antenna because of the need for the magnetic film layers between the antenna coils.
Another problem with the approach as taught in U.S. Pat. Nos. 4,857,893 and 4,724,427 is the attendant integrating of an antenna on an integrated circuit (IC) chip. In the case of an antenna disposed about the periphery of the chip, as described by the patents discussed hereinabove, the location of the antenna interferes with conventional bond pad layout about the periphery of the chip. Also, the electromagnetic fields within the central area of an antenna laid out about the periphery of a chip can interfere with the operation of circuits located within the antenna.
U.S. Pat. Nos. 6,373,447 discloses the use of one or more antennas that are formed on an integrated circuit chip connected to other circuitry on the chip. The antenna configurations include loop, multi-turned loop, square spiral, long wired and dipole. The antenna could have two or more segments which could selectively be connected to one another to alter effective length of the antenna. Also, the two antennas are said to be capable of being formed in two different metallization layers separated by an insulating layer.
U.S. Pat. No. 6,373,447 attempts to overcome the problems of U.S. Pat. Nos. 4,857,893 and 4,724,427 by having the antenna formed on other than a peripheral area of an integrated circuit (IC) chip. U.S. Pat. No. 6,373,447 describes devices comprising an integrated circuit (IC) chip having a surface wherein the surface is divided into a peripheral area and a central area. The central area comprises a first portion and a second portion wherein the circuitry of the IC chip is disposed within the first portion of the central area; and an antenna disposed within the second portion of the central area. This patent teaches that one or more antennas can be formed on an integrated circuit chip connected to other circuitry on the chip. The antenna configurations include loop, multi-turned loop, square spiral, long wired and dipole. The antenna could have two or more segments which could selectively be connected to one another to alter the effective length of the antenna.
U.S. Pat. No. 6,373,447 attempts to avoid the problems of the antenna interfering with the conventional bond pad layout about the periphery of the chip by placing the antenna in the central area of the chip. However, in all cases disclosed by the inventor the antenna is located in one portion of the central area, and IC circuitry is disposed on the other portion of the central area. The inventors do state in the body of the patent that the antennas can also be located on “one or two or three (but not four) edges of the chip, so long as there are no bond pads in that area”.
A problem with the prior art as discussed above is that disposition of the antenna on the chip is limited to specific different parts of the chip. In the case of U.S. Pat. Nos. 4,857,893 and 4,724,427 the antenna is on the periphery of the chip and in the case of U.S. Pat. No. 6,373,447 the antenna is in the central area of the chip.
A further problem with the antenna on chip designs as disclosed by prior art is that the antenna and IC circuitry are disposed as discrete components in separate portions of the chip to minimize the interaction of the antenna and the circuitry of the IC chip. In the case of U S. Pat. No. 6,373,447, the antenna is one portion of the central area and the IC circuitry is the other portion of the central area. This again limits the design of placing an antenna on a IC chip. Furthermore, it makes for devices that are not truly integrated.